The present invention relates to digital communications. More specifically, it relates to reception of a Frequency Shift Key (FSK) signal on a digital connection.
Frequency Shift Keying (FSK) is a data modulation scheme commonly used in digital communications. FSK has been recommended as a low speed modulation format for numerous standards for the Public Switched Telephone Network (PSTN) by both national and international standards organizations. Examples of standards that recommend FSK are Bell 103, Bell 202, ITU-T V.21, ITU-T V.23, and ITU-T V.91.
FSK possesses several characteristics that make it useful for communication systems. It is a simple modulation method that is a commonly used approach to the exchange of additional low speed information in high speed communication systems. For instance, FSK is used when call waiting caller ID information is transmitted during a voice or data connection.
FSK is also used to exchange ITU-T V.8bis modem negotiation protocol messages as part of the V.91 negotiation procedure. V.91 defines a protocol between two modems that are connected through a 4-wire digital connection. The V.8 modem negotiation protocol is required for the identification and selection of common modes of operation over the 4-wire digital connection between the modems over the PSTN. Typically, reception of FSK signals is performed by digital processing algorithms. These algorithms may require extra processing power and may require the use of a digital signal processor (DSP).
In these applications, the computational complexity and memory requirements for demodulating of the FSK signal are very important. If an FSK reception algorithm requires additional hardware to perform the computation needed to decode the signal, then the algorithm is not suitable for low-cost devices that have limited computing resources.
It is well understood in the art that FSK can be detected using either a non-coherent method employing a frequency detector or a coherent method that utilizes a pair of product detectors.
FIG. 1 illustrates a generalized example of a coherent FSK receiver 10. The receiver 10 receives a received signal r(t) that is composed of a data signal s(t) and a noise signal n(t). The data signal s(t) is composed of mark (binary 1) and space (binary 0) signals s1(t) and s0(t), respectively. The mark signal s1(t) can be described as s1(t)=A cos(xcfx891t+xcex8c), where xcfx891=2xcfx80f1 and f1 is the frequency that represents a binary 1 in the FSK encoding scheme. The space signal s0(t) can be described as s0(t)=A cos(xcfx890t+xcex8c), where xcfx890=2 xcfx80f0 and f0 is the frequency that represents a binary 0 in the FSK encoding scheme. In the FSK scheme described, f1 greater than f0 and the data frequency shift of s(t) is xcex94F=f1xe2x88x92f0 around a center frequency fc of the FSK data signal s(t).
The receiver 10 includes an upper channel product detector 12 and a lower channel product detector 14, which each receive r(t). The upper channel product detector 12 receives a first coherent reference signal 2 cos(xcfx891t+xcex8c) at one input terminal and r(t) at a second input terminal. The lower channel product detector 14 receives a second coherent reference signal 2 cos(xcfx890t+xcex8c). Note here that, in coherent FSK detection, it is necessary to know the phase xcex8c of the received sinusoidal signal in order to build the coherent reference signals 2 cos(xcfx891t+xcex8c) and 2 cos(xcfx890t+xcex8c).
The output of the lower channel product detector 14 is input to a negative terminal of summer 16 and the output of the upper channel product detector 12 is input to a positive terminal of summer 16. Summer 16 will subtract the lower channel output from the upper channel output in order to produce a difference signal at an output terminal of the summer. This difference signal is then input to a low pass filter (LPF) 18.
LPF 18, which can also be viewed as a matched filter, when combined with the frequency translation performed by product detectors 12 and 14, function as dual bandpass filters. Thus, the input noise n(t) that affects the output of receiver 10 consists of two narrowband components n1(t) and n0(t) centered at f1 and f0, respectively. The bandwidth B of LPF 18 is less than the frequency difference xcex94F, such that 2xcex94F greater than 2B, where the effective bandwidth Bp is 2B, and the filtering action of LPF 18 separates the mark and space signals s1(t) and s0(t) in order to produce a baseband analog output signal ro(t).
The baseband analog output signal ro(t) is {+A for a binary 1; xe2x88x92A for a binary 0} +no(t). This signal is input to sample and hold 20 that obtains a discrete signal ro(to) that is then input to threshold comparator 22 for comparison to threshold VT. Because of the symmetry of the baseband analog output signal ro(t), i.e. a binary 1 is +A and a binary 0 is xe2x88x92A, and because the noise in each of the upper and lower channels is similar, i.e. white Gaussian noise, the optimum threshold for VT is 0. The threshold comparator 22 then outputs a digital output signal m(t) that reflects the data signal s(t) along with the noise signal n(t).
Note that the coherent FSK receiver requires that a coherent reference signal be obtained. The reference recovery circuitry required to recover the coherent reference is typically complex and expensive. Also, the coherent reference is often extracted from the noisy received FSK signal so that the reference itself contains noise. Also, the reference recovery circuitry required to recover the coherent reference is typically complex and expensive. As a consequence, a non-coherent receiver is often used to avoid the coherent reference recovery circuitry.
FIG. 2 illustrates a generalized noncoherent FSK receiver 30. Receiver 30 receives signal r(t) that is input to an upper channel detector 32 and a lower channel detector 42. The upper channel detector 32 is configured to detect the mark signal and is composed of a bandpass filter 34 centered on f1 connected in series with an envelope detector 36. Envelope detector 36 outputs an upper channel output signal vU(t) that is input to a positive input terminal of summer 38.
The lower channel detector 42 is configured to detect the space signal and is composed of a bandpass filter 44 centered on f0 connected in series with an envelope detector 46. Envelope detector 46 outputs a lower channel output signal vL(t) that is input to a negative input terminal of summer 38.
The analog output signal ro(t) from summer 38 is positive when the upper channel output signal vU(t) exceeds the lower channel output signal vL(t). A mark signal can be viewed as the signal value of vU(t) for a mark less the signal value of vL(t) for a mark or {+A+n1(t)}xe2x88x92{0+n0(t)}. Similarly, ro(t) from summer 38 is negative when the lower channel output signal vL(t) exceeds the upper channel output signal vU(t). Thus, a space signal can be viewed as the signal value of vL(t) for a space less the signal value of vU(t) for a space or {xe2x88x92A+n0(t)}xe2x88x92{n1(t)}. Noncoherent FSK detection requires only 1 dB of additional signal-to-noise ratio (Eb/N0) over coherent FSK detection. However, in noncoherent FSK detection, it is unnecessary to generate a coherent reference signal and it is therefore unnecessary to know the phase xcex8c of the received sinusoidal signal. An estimate of the phase information can be obtained using a phase locked loop (PLL) circuit. However, it is difficult to obtain a phase estimate in a digital receiver, particularly when the number of samples per binary bit is small because a phase estimate typically requires more than ten samples in order to converge. The Bell 202 and ITU-T V.23 standards, for example, set forth a requirement of only six samples per binary bit. Thus, noncoherent FSK receivers can be simpler to construct than coherent FSK receivers. However, in real systems, it is difficult to obtain relatively low bit error rate performance with noncoherent FSK detection.
FIG. 3 illustrates another generalized embodiment of a FSK demodulation receiver 60 that operates on a probabilistic method of demodulation. The probabilistic receiver 60 receives received data signal r(t) which is input to four different channels. The first channel is composed of product detector 62, integrator 64, sampling switch 66 and squaring operator 68 connected in series, where product detector 62 multiplies the received signal r(t) by cos 2xcfx80fct. An output of squaring operator 68 is connected to a first input to adder 70. Likewise, the second channel is composed of product detector 72, integrator 74, sampling switch 76 and squaring operator 78 connected in series, where product detector 72 multiplies the received signal r(t) by sin 2xcfx80fct. An output of squaring operator 78 is connected to a second input to adder 70.
The third channel is composed of product detector 82, integrator 84, sampling switch 86 and squaring operator 88 connected in series, where product detector 82 multiplies the received signal r(t) by cos 2xcfx80(fc+xcex94J)t. An output of squaring operator 88 is connected to a first input to adder 90. Likewise, the fourth channel is composed of product detector 92, integrator 94, sampling switch 96 and squaring operator 98 connected in series, where product detector 92 multiplies the received signal r(t) by sin 2xcfx80(fc+xcex94f)t. An output of squaring operator 98 is connected to a second input to adder 90.
Each of the sample switches 66, 76, 86 and 96 receives a sampling signal fs that periodically closes the switches in order to obtain an instantaneous sample of the detected signal in each channel. The sample signal fs has a sample time T that must be recovered from the received signal r(t) using clock recovery circuitry.
The value of xcex94f=1/T of the sample time T such that the product detectors 82 and 92 for the third and fourth channels, respectively, detect a signal orthogonal to the signal detected by the product detectors 62 and 72, respectively, for the first and second channels. Note that the coefficients for product detectors 62, 72, 82 and 92 are all time varying and must therefore be constantly changed. The integrators 64, 74, 84 and 94 for each of the four channels of receiver 60 continuously integrate the detected signal of their respective product detectors from a beginning time instant for the signal detection of r(t) to a present time instant.
An output of adder 90 is subtracted from an output of adder 70 by subtractor 80 in order to obtain a decision value that is independent of the phase of the received signal. The receiver 60 selects the data signal, i.e. the mark frequency f1 or the space frequency f0, having the highest probability of having been sent by detecting the signal having the largest envelope value.
To obtain good performance from receiver 60, the sample rate fs must be devisable by both the mark frequency f1 and the space frequency f0. If this condition is not met, performance can degrade badly. However, the sample rate typically cannot be a multiple of both these frequencies. For example, ITU-T V.23 specifies a mark frequency of 1300 Hz and a space frequency of 2100 Hz while the sample rate is typically 7200 Hz, which is neither a multiple of 1300 Hz nor 2100 Hz.
Consequently, the need remains for a cost-effective FSK reception method.
In accordance with preferred embodiments of the present invention, some of the problems associated with conventional FSK receivers are overcome.
One aspect of the invention is a receiver for receiving a FSK signal having a first frequency corresponding to a binary xe2x80x9c0xe2x80x9d and a second frequency corresponding to a binary xe2x80x9c1xe2x80x9d, where the receiver includes a finite series of delay elements, each element having an input and an output terminal and being configured to introduce a predetermined delay interval corresponding to a sampling period of the received signal, and where the input terminal of a first element of the finite series of delay elements is coupled to an input terminal of the receiver. An arithmetic unit of the receiver has a plurality of input terminals and an output terminal, where a first one of the plurality of input terminals is coupled to the input terminal of the first element of the finite series of delay elements and where each remaining one of the plurality of input terminals is coupled to the output terminal of a corresponding one of the delay elements, where the arithmetic unit is configured to generate a metric signal at the output terminal of the arithmetic unit using a phase independent equation. The receiver also has an integration and decision unit having an input terminal coupled to the output terminal of the arithmetic unit, where the integration and decision unit is configured to compare the metric signal to a threshold value to obtain a binary sample and integrate multiple binary samples in a baud interval of the FSK signal in order to generate a binary data signal at an output terminal of the integration and decision unit.
Another aspect of the present invention is a method for decoding a received signal having a first frequency representing a binary xe2x80x9c0xe2x80x9d and a second frequency representing a binary xe2x80x9c1xe2x80x9d. The method according to the present invention includes sampling the received signal at a predetermined sample rate to obtain samples of the received signal and producing a series of equidistant samples by delaying the samples of the received signal. A phase independent trigonometric equation is used to generate an estimated value from the series of equidistant samples. Then, the estimated value is compared to a threshold value in order to generate a binary value corresponding to the estimated value. The method also calls for integrating each binary value generated in a baud interval in order to output a binary bit of a data signal.